There are several applications in which in an electronic device it is required to wait for a pre-set time, which may even have a long duration (minutes or hours). It may further be required for this wait time to be measured also in the case where the electronic device is in a state where it is turned off, de-activated, or blocked.
For example, in secure microcontrollers (the so-called secure MCUs) applications, e.g., for operations of authentication, communication, or secure information storage, when an attack is detected aimed at stealing sensitive information; the electronic device in which the secure microcontroller is used is set in a disabled state.
Typically, in case of repeated attacks, the electronic device is set in a definitive disabled state for protecting the sensitive information. However, this defensive behavior entails subsequent impossibility for the user to operate the electronic device.
It is thus preferable to set the electronic device in a blocking state for a time sufficiently long (minutes or hours) for preventing the attack from being successful (it is difficult to violate the device if, after an attack, it is necessary to wait for a long period of time to unblock the same electronic device), at the same time preserving the possibility for the user to continue to operate the device.
For this purpose, a long-time-constant circuit stage (in what follows “LTC stage”) is used, basically constituted by a charge-retention electronic circuit, which defines an extremely long RC time constant for discharge of a previously stored electric charge (this time constant determines the wait time interval prior to restoring functionality of the electronic device). The resistance defining the RC time constant may have, for example, values of the order of PΩ (1015Ω) for defining a discharge time of the order of minutes or even hours.
The LTC stage may moreover be set (programmed), or reset (erased), by applying appropriate biasing signals.
An LTC stage is described, for example, in US 2015/0043269, which is incorporated herein by reference. This LTC stage is illustrated in FIG. 1, where it is designated by 1, and is basically a charge-retention electronic circuit for time measurement, including a capacitive charge-storage element in which discharge occurs by a slow process of leakage through the dielectric space of the same capacitive element.
In particular, the LTC stage 1 comprises: a storage capacitor 2, coupled between a first biasing terminal 3a, set in use at a first biasing voltage V1, and a floating node 4; a transfer capacitor 5, coupled between a second biasing terminal 3b, set in use at a second biasing voltage V2, and the floating node 4; and a discharge element 6, coupled between the same floating node 4 and a reference terminal 7, set in use at a reference voltage or ground (gnd).
In particular, the discharge element 6 is formed by a plurality of elementary discharge units 8, which are coupled together in series between the aforesaid floating node 4 and the aforesaid reference terminal 7 and define between them a plurality of intermediate nodes Ni (where i is an integer corresponding to the number of elementary discharge units 8, minus one).
As described in detail in the aforesaid document US 2015/0043269 A1, each elementary discharge unit 8 comprises a first electrode and a second electrode (made, for example, of polysilicon), arranged between which is a thin dielectric layer, through which a transfer of charges by the tunnel effect occurs. The connection in series between the various elementary discharge units 8 is implemented by the coupling between the first electrode or the second electrode of consecutive elementary discharge units 8 in the series.
The floating node 4 is kept floating, i.e., isolated, separated by a dielectric space, from the terminals where the voltage is applied and is not directly coupled to any non-isolated region of the substrate of semiconductor material in which the LTC stage 1 is provided.
The capacitance C1 of the storage capacitor 2 (for example, comprised between 1 and 100 pF) is much higher than the capacitance C2 of the transfer capacitor 5 (for example, comprised between 0.01 and 50 pF); moreover, the thickness of the dielectric layer of the storage capacitor 2 (for example, comprised between 150 and 200 Å), made, for example, of oxide-nitride-oxide (ONO) dielectric, is greater than the respective thickness of the transfer capacitor 5 (for example, comprised between 70 and 100 Å), made of tunnel oxide.
Basically, the function of the storage capacitor 2 is on the one hand, to enable for the LTC stage 1 to have a good coupling coefficient to favour the Fowler-Nordheim mechanism (tunnel effect) for the set and reset operations (storage and removal of charges in and from the floating node 4), and, on the other, to constitute the most significant part of the capacitance in the time constant. The function of the transfer capacitor 5 is to enable injection, or extraction, of charges into, or from, the floating node 4, coupled to which is also the storage capacitor 2, in particular by the tunnel effect, in a way altogether similar to what occurs for the floating-gate terminal of a non-volatile memory.
Each of the elementary discharge units 8 has characteristics, for example in terms of thickness of the corresponding dielectric layer, such as to have a non-negligible charge leakage over time, through the corresponding dielectric space. Furthermore, the overall resistance of the discharge element 6, defined jointly by the various elementary discharge units 8, is extremely high, for example of the order of TΩ or PΩ.
The function of the discharge element 6 is to discharge in a controlled way, in a sufficiently long time interval (of the order of minutes or hours), the charge stored in the capacitor constituted by the parallel of the storage capacitor 2 and transfer capacitor 5.
In use, in the LTC stage 1 the following operations may be envisaged. A programming operation, the so-called set operation, can be performed for initialization of the charge in the storage capacitor 2, by applying a high potential difference, for example of a positive value, between the first and second biasing terminals 3a, 3b, and a consequent injection of electric charges through the transfer capacitor 5. For example, a high positive voltage +HV (boosted with respect to a logic supply voltage, for instance, via a charge-pump stage) is applied on the first biasing terminal 3a, and a high negative voltage −HV is applied on the second biasing terminal 3b. 
An operation of reset, or erasure, of the charge stored in the storage capacitor 2 can be performed by applying a high potential difference, for example of a negative value, between the first and second biasing terminals 3a, 3b, and a consequent extraction of charges through the transfer capacitor 5. For example, the high negative voltage −HV is applied on the first biasing terminal 3a, and the high positive voltage +HV is applied on the second biasing terminal 3b. 
An operation of reading of the residual charge present in the storage capacitor 2, by detecting the voltage on the floating node 4, or on one or more of the intermediate nodes Ni, during discharge of the charge stored in the storage capacitor 2 (that was stored in a previous programming operation). This discharge occurs through the discharge element 6, with the first and second biasing terminals 3a, 3b set at ground, the discharge time constant RC being the product of the resistance of the discharge element 6 and of the overall capacitance of the storage capacitor 2 and transfer capacitor 5 (which are coupled in parallel together and to the discharge element 6).
As shown in greater detail in FIG. 2, a reading circuit 9 of the LTC stage 1 comprises an operational amplifier 10 (in particular an operational transconductance amplifier—OTA), operating as a comparator, which has a first input terminal 10a, for example the negative input terminal, coupled to the floating node 4, a second input terminal 10b, in the example the positive input terminal, receiving a comparison reference voltage Vx, of an appropriate value (generated in a per se known manner starting from a supply voltage), and an output 10c, which supplies an output voltage Vout, the value of which is indicative of the residual charge in the storage capacitor 2.
In particular, if the reading voltage VL on the floating node 4 has a given relation with the comparison reference voltage Vx (for example, being lower or higher than the same comparison reference voltage Vx), the discharge of the storage capacitor 2 may be considered completed (for example, for the purpose of unblocking the electronic device that had previously been blocked due to detection of an attack attempt).
The value of the comparison reference voltage Vx is thus chosen for setting the desired duration of the discharge interval also as a function of the value assumed by the reading voltage VL on the floating node 4 at the end of the programming step (or at the start of the reading step).
Likewise, as shown schematically in the aforesaid FIG. 1, further comparator stages (designated by 10i) may be provided, coupled to one or more of the intermediate nodes Ni, in order to detect the voltage on the intermediate nodes Ni and compare it with a respective reference voltage.
The present Applicant has realized that the operation of reading the residual charge in the LTC stage 1 has a number of problems, which may render difficult its implementation.
In the first place, both positive charges (in which case the discharge evolves from a positive reading voltage to ground) and negative charges (in which case, the discharge evolves from a negative reading voltage to ground) may be stored in the storage capacitor 2. In fact, for reasons of reliability, it may in general be required that the charge stored in the storage capacitor 2 is also negative.
It is thus required for the reading circuit 9 to be able to operate also with negative reading voltages VL, which entails, as it is shown in the aforesaid FIG. 2, the operational amplifier 10 having a first supply input 10d and also a second supply input 10e, receiving, respectively, a positive supply voltage Vcc (>0) and a negative supply voltage Vss (<0). In addition, also the reference voltage Vx should be able to assume negative values (requiring, for example, a purposely provided charge-pump stage for its generation).
In general, the presence of negative reading voltages VL thus entails an increase in the circuit complexity, and a corresponding increase in the area occupation in the integrated embodiment, as well as an increase in the electric-power consumption.
Moreover, in a known way, the need to set the negative circuitry (for example, for generation of the negative-voltage references) requires an increase in the latency times prior to execution of the reading operation, and thus prevents high reading speed from being reached.
A further problem that afflicts the reading circuit 9 is linked to the fact that, when the electronic device in which it is incorporated is off (in so-called “power off” conditions), discharge paths towards ground (for example, constituted by leakage paths of the junctions of MOS transistors) may be generated, for example within biasing circuits (of a known type, here and not illustrated) coupled to the biasing terminals 3a, 3b; these discharge paths may affect the discharge time constant RC of the LTC stage 1, modifying it. In fact, the resistance towards ground constituted by the alternative leakage discharge paths may in general be comparable with the resistance of the discharge element 6 of the LTC stage 1.
Basically, a significant spread of the value of the time constant may arise, on account of the aforesaid alternative leakage discharge paths in power-off condition.